9/21/2020 0 Comments Synopsys License Generator
The Chipyard framework can compile and execute simulations using VCS.VCS simulation will generally compile faster than Verilator simulations.This will elaborate the RocketConfig in the example project.
Synopsys Simulator That HasThis executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. Otherwise, you will likely encounter a Makefile target error. Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog). For example, in the normal case, the MODEL variable specifies the TestHarness as the top-level of the design. However, the true top-level design, the SoC being simulated, is pointed to by the TOP variable. This separation allows the infrastructure to separate files based on the harness or the SoC top level. Therefore, in order to simulate a simple Rocket-based example system we can use. For example, the following code example will run the RISC-V assembly benchmark suite on the Hwacha subproject. Specifically, the SoC top-level ( TOP ) Verilog file is denoted with.top.v while the TestHarness file is denoted with.harness.v. If you have Synopsys licenses, we recommend using the DVE waveform viewer.
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